1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and a method for controlling a delay path, and more particularly to a semiconductor integrated circuit device for performing signal transmission between two circuits, and a method for controlling a delay path included therein.
2. Description of Related Art
When a logic circuit is constructed on the semiconductor integrated circuit device, a design is made to satisfy the conditions of a setup time and a hold time in terms of a delay time, taking variation of the devices into consideration in the worst cases. For example, a circuit that changes a transistor size, a threshold voltage, a gate type, the number of gate stages, or the like in a CMOS circuit to provide an appropriate delay time is inserted between two synchronous operation circuits that operate in synchronism with a clock signal so as to satisfy the condition of the hold time.
As a delay circuit inserted between the two synchronous operation circuits, for example, a stable delay time can be obtained with the use of the combination of a normal CMOS circuit with a DCVSL (differential cascade voltage switch logic) disclosed in non-patent document 1.
As a related art, patent document 1 discloses a redundant circuit device in which when a setting state is off in any system of a plurality of digital processor circuits, even if any one of the digital processor circuits in the normal systems is stopped, the validity of a majority vote result is ensured to maintain the reliability of the normal operation.    [Non-patent Document 1] Kan M. Chu and David L. Pulfrey, “A Comparison of CMOS Circuit Techniques: Differential Cascade Voltage Switch Logic Versus Conventional Logic,” IEEE Journal of Solid-state Circuits, vol. SC-22. pp. 528-532, August 1987    [Patent Document 1] Japanese Patent Application Laid Open No. 2008-191939